Business Wire

Imec and Cadence Tape Out Industry’s First 3nm Test Chip

LEUVEN, Belgium & SAN JOSE, Calif.--(BUSINESS WIRE)--The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. (NASDAQ: CDNS) ...
Design-Reuse

Cadence Solutions Enable Successful Tape Out of 20-Nanometer SoC Test Chip by Global Unichip Corporation

SAN JOSE, CA-- Jul 9, 2013-- Cadence Design Systems, a leader in global electronic design innovation, today announced that the design services company, Global Unichip Corporation (GUC), utilized the ...
Business Wire

Cadence Collaboration With Arm Enables Customers to Successfully Tape out Next-Generation Arm Mobile Designs

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that through a collaboration with Arm, customers have successfully taped out mobile SoCs using Cadence ® ...
Design-Reuse

ARM and Cadence Tape Out First 14nm FinFET Test Chip Targeting Samsung Process

CAMBRIDGE, United Kingdom, and SAN JOSE, Calif., Dec. 20, 2012 - ARM (LON: ARM; Nasdaq: ARMH) and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the tape-out of the first 14-nanometer ...
Electronic Design

imec, Cadence tape-out industry’s first 3-nm test chip

Leuven, Belgium, and San Jose, CA. imec and Cadence Design Systems have announced that their extensive, long-standing collaboration has resulted in the industry’s first 3-nm test chip tapeout. The ...