Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

Marvin Test Solutions expands user-programmable PXIe FPGA product line

IRVINE, CA—Marvin Test Solutions, Inc., a provider of globally-deployed innovative test solutions for military, aerospace, and manufacturing organizations, has announced the release of the new GX3800e ...
Electronic Design

GOEPEL Extends ChipVORX to Xilinx Kintex7 FPGA Series

October 29, 2013. GOEPEL electronic has introduced a special IP model library for the Xilinx Kintex7 FPGA family, thereby enabling ChipVORX technology utilization for FPGA assisted test and ...
EDN

Internal test in FPGA design

http://www.xilinx.comAs the density of field-programmable-gate arrays (FPGAs) continues to increase, engineers are challenged to come up with ways to test and verify ...
Semiconductor Engineering

Software Driven Test Of FPGA Prototype

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real ...
EDN

FPGA/DSP-development kit features RTL and model-based support

The Avnet Electronics Marketing operating group of Avnet Inc is now accepting orders for its $1995 Xilinx Spartan-6 FPGA/DSP-development kit. The kit includes a device-locked version of Xilinx's ISE ...