New reports on U.S. IC chemicals and materials availability; China export blacklist expands; global fab equipment report; ...

Verifying the functionality of a full multi-chip system, including digital controllers, analog electrical, and photonic ...

The chip industry is exploring multiple avenues for simplifying multi-die integration, but difficulties remain for optimizing ...

Number of designs that are late increases. Rapidly rising complexity is the leading cause, but tools, training, and workflows ...

L-R: Cadence’s Young; Synopsys’ Stahl; Siemens’ Munsey; ChipAgents’ Wang; Theodore Wilson. SE: What is a digital twin in the ...

The founders of EDA are retiring, and perhaps it’s time that EDA headed off in a different direction.

The semiconductor industry is on the brink of a major transformation. While AI-driven verification and connected workflows ...

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip ...

Chiplets are the only viable solution to maintain the annual cadence of hardware upgrades that AI scaling demands.

Semiconductor verification is changing to integrate AI with human expertise.

In a blog for SEMI, Melissa Dahlin of Policy Equity Group argues that childcare should be an important part of workforce ...

HW/SW co-verification is becoming incredibly challenging. A way to cross the boundaries between UVM-based tests and C-tests in an organized and seamless way is called for. PSS is the best language and ...